ASynchronous, open source, Processor IP of the DLX Architecture. Goal: show feasibility to design and deliver asynchronous open IPs in portable, re-usable way. Information, downloads. Open source hardware.

Book review, explains that book is a classic and standard work in its field. Ars Technica.

By John L. Hennessy, David A. Patterson; Morgan Kaufmann, 2007, ISBN 9780123704900, 4th edition. Design in quantitative terms, in context of real running systems, not abstract formats; how technology changes in time, empirical constants needed in design.

Director of Northeastern University Computer Architecture Research Laboratory, and co-author of Computer Architecture: A Quantitative Approach. Professional information with some links.

Introductory HTML slide show.

Photo with descriptions.

Documents DLX implementation by Microsystems Prototyping Laboratory (MPL), MSU Engineering Research Center; used as design driver to help validate standard cell libraries.

VHDL model of processor; most instructions use 5 clock cycles to run, jumps use 3, floating point timing not fully accurate because fp instructions also take 5 cycles to run; description, download.

Documents: getting started, instruction set summary and description, simulator manual.

Tables of instructions, categorized, as PDF slides. By Guy Even, Tel Aviv University.